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74LVT162245 * 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25 Series Resistors in A Port Outputs
January 1999 Revised November 1999
74LVT162245 * 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25 Series Resistors in A Port Outputs
General Description
The LVT162245 and LVTH162245 contains sixteen noninverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The LVT162245 and LVTH162245 are designed with equivalent 25 series resistance in both the HIGH and LOW states on the A Port outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH162245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These non-inverting transceivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT162245 and LVTH162245 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pullup resistors to hold unused inputs (74LVTH162245), also available without bushold feature (74LVT162245). s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s A Port outputs include equivalent series resistance of 25 making external termination resistors unnecessary and reducing overshoot and undershoot s A Port outputs source/sink 12 mA. B Port outputs source/sink -32 mA/+64 mA s Functionally compatible with the 74 series 162245 s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number 74LVT162245MEA (Note 1) 74LVT162245MTD (Note 1) 74LVTH162245MEA 74LVTH162245MEX (Note 2) 74LVTH162245MTD 74LVTH162245MTX (Note 2) Package Number MS48A MTD48 MS48A MS48A MTD48 MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBE] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL]
Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Note 2: Use this Order Number to receive devices in Tape and Reel.
(c) 1999 Fairchild Semiconductor Corporation
DS012446
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74LVT162245 * 74LVTH162245
Logic Symbol
Pin Descriptions
Pin Names OEn T/Rn A0-A15 Description Output Enable Input (Active LOW) Transmit/Receive Input Side A Inputs/3-STATE Outputs Side B Inputs/3-STATE Outputs
Connection Diagram
B0-B15
Truth Tables
Inputs OE1 L L H Inputs OE2 L L H T/R2 L H X Bus B8-B15 Data to Bus A8-A15 Bus A8-A15 Data to Bus B8-B15 HIGH-Z State on A8-A15, B8-B15 T/R1 L H X Bus B0-B7 Data to Bus A0-A7 Bus A0-A7 Data to Bus B0-B7 HIGH-Z State on A0-A7, B0-B7 Outputs Outputs
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Functional Description
The LVT162245 and LVTH162245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVT162245 * 74LVTH162245
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value -0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50 64 128 64 128 -65 to +150 Output in 3-STATE Output in HIGH or LOW State (Note 4) VI < GND VO < GND VO > VCC VO > VCC Output at HIGH State Output at LOW State Conditions Units V V V mA mA mA mA mA C
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA t/V Supply Voltage Input Voltage HIGH-Level Output Current LOW-Level Output Current Free Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V B Port A Port B Port A Port -40 0 Parameter Min 2.7 0 Max 3.6 5.5 -32 -12 64 12 +85 10 Units V V mA mA C ns/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed.
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74LVT162245 * 74LVTH162245
DC Electrical Characteristics
Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage A Port B Port VOL Output LOW Voltage A Port B Port VCC (V) 2.7 2.7-3.6 2.7-3.6 3.0 2.7-3.6 2.7 3.0 3.0 2.7 2.7 3.0 3.0 3.0 II(HOLD) (Note 5) II(OD) (Note 5) II Bushold Input Minimum Drive Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH IOZH+ ICCH ICCL ICCZ ICCZ+ ICC Power Off Leakage Current Power Up/Down 3-STATE Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 8)
Note 5: Applies to Bushold versions only (74LVTH162245). Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
TA = -40C to +85C Min Max -1.2 2.0 0.8 2.0 VCC-0.2 2.4 2.0 0.8 0.2 0.5 0.4 0.5 0.55 75 -75 500 -500 10 1 -5 1 100 100 -5 -5 5 5 10 0.19 5 0.19 0.19 0.2 A A A V Units V V V V V V V V Conditions II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -12 mA IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 12 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 64 mA VI = 0.8V VI = 2.0V (Note 6) (Note 7) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC A A A A A A A mA mA mA mA mA 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND to VCC VO = 0.5V VO = 0.0V VO = 3.0V VO = 3.6V VCC < VO 5.5V Outputs HIGH Outputs LOW Outputs Disabled VCC VO 5.5V, Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND
3.0 3.0 3.6 3.6 3.6 0 0-1.5V 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
IOZL (Note 5) 3-STATE Output Leakage Current IOZH (Note 5) 3-STATE Output Leakage Current
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL
(Note 9)
TA = 25C Units Min Typ 0.8 -0.8 Max V V Conditions CL = 50 pF RL = 500 (Note 10) (Note 10)
VCC (V) 3.3 3.3
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
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74LVT162245 * 74LVTH162245
AC Electrical Characteristics
TA = -40C to +85C CL = 50 pF, RL = 500 Symbol Parameter VCC = 3.3V 0.3V Min tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tOSHL tOSLH tOSHL tOSLH A Port Output to Output Skew (Note 11) B Port Output to Output Skew (Note 11) Output Disable Time for B Port Output Output Disable Time for A Port Output Output Enable Time for B Port Output Output Enable Time for A Port Output Propagation Delay Data to B Port Output Propagation Delay Data to A Port Output 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.5 1.5 1.5 Max 4.0 3.7 3.5 3.5 5.3 5.6 4.6 5.3 5.6 5.5 5.4 5.1 1.0 1.0 VCC = 2.7V Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.5 1.5 1.5 Max 4.6 4.1 3.9 3.9 6.3 7.2 5.4 6.9 6.3 5.5 6.1 5.4 1.0 1.0 Units
ns ns ns ns ns ns ns ns
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance
Symbol CIN CI/O
(Note 12)
Parameter Conditions VCC = 0V, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Input Capacitance Input/Output Capacitance
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74LVT162245 * 74LVTH162245
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74LVT162245 * 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25 Series Resistors in A Port Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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